The present invention concerns a procedure for transferring data between central units or processors in a multiple processor system comprising one or several central units with memories.
In multiprocessor systems most often two different techniques have been employed towards inter-processor data transfer: one is called the I/O technique and the second, the DMA technique. In the traditional I/O technique (Input/Output Technique) the processor reads the data sent by another processor one word or byte at a time and stores them in its memory, respectively reads one word or byte at a time from its memory and writes them to the other processor over a data transfer bus between them. Moreover, if the data transfer is fast, the writing processor must make sure that the reading processor has had time to read the preceding data before the next is written. This way of managing data transfer is comparatively slow owing to the fact that the processors have to perform several different operations in order to transfer one word or byte to the other. In addition, the use of the I/O technique slows down the execution of the processors' other programs because for the duration of said operations the execution of other programme has to be suspended, which furthermore necessitates extra processor state storings and returns. The I/O technique is usable only in data transfer events which are either slow or have a limited quantity.
The other way in which to manage inter-processor data transfer is the DMA (Direct Memory Access) technique, in which data are transferred from or to the processor's memory without any actual participation of the processor itself in the transfer event proper. This is most often implemented in that the processors participating in the transfer operation are stopped for the duration of the transfer event. One avoids in this way the extra storing and recalling operations occuring in the I/O technique and, moreover, the transfer may be fast because it can be carried out by a logic circuit made exactly for this purpose. In other words, the logic does not e.g. read and record; instead, it directly stores the arriving data in the memory. This mode however requires a fairly complex logic circuitry and therefore this technique is expensive. Furthermore, if the need of data transfer is high, the logic circuit begins to slow down the operation of the processor because the interruption times increase in length or they are repeated at a higher frequency. The same occurs when there are several processors writing to or reading from the same memory, because transfer in this manner is usually only possible between two processors at any one ttime. By the DMA technique such constructions have also been carried out in which the inter-processor data transfer takes place over a joint memory. The system in this case includes a memory which can be written to by all processors and which can be read by them, but this memory cannot be used but by one processor at the time, whence follows that any processor--or the DMA technique at least--has to await the termination of data transfer by the other logic circuit or circuits or processor/processors. It is possible in this way to deduct part of the interruptions caused by the DMA in the interfacing of more than two processors, but it is still possible that waiting for the transfer event proper becomes necessary. Other drawbacks of the DMA technique are its wide bus and the fast data transfer signals, which introduce a poor interference tolerance. The DMA technique is usable when the requirements of data transfer is high and there are not many pieces of apparatus needing simultaneous data transfer.
The purpose of the procedure and apparatus of the present invention is to eliminate the drawbacks mentioned and to provide a reliable and economical data transfer system in a multi-processor system.